In a data transmission system events may be monitored for diagnostic purposes or in order to optimize a system's efficiency. In the past, to count a plurality of system events, an individual storage register or counter was allocated for each type of event to be counted. The count value for each monitored event is stored in an individual register and during one clock cycle, the stored count value to be incremented is read out of each memory and incremented. Although all of the count values may be incremented simultaneously during one clock cycle, multiple counter registers are necessary, thereby occupying valuable space on an integrated circuit chip.
Storage registers, memories, prioritizer units, incrementors and counting systems are all well known. However, none of the conventional systems disclose a single memory based event counter system which prioritizes a plurality of input signals and generates a signal that is used to access the single memory device where the system counters are stored. While the prior art may reveal individual elements which may perform specific functions, it does not teach or suggest combining the elements to achieve a memory based event counter in accordance with the present invention.
For example, U.S. Pat. No. 3,701,109, titled, "Priority Access System," and issued on Nov. 9, 1970 to Theodore Peters, discloses an apparatus which prioritizes a plurality of users into one of N groups. The priority assigned to each group is based upon the extent and nature of usage by the users within each group. Within a group the priority assigned to each user for accessing a computer, for example, is the same and the users in a group sequentially access the computer The system has a random access memory (RAM) for storing the number of times a given group is accessed during a particular time period and an incrementor which increments this number and stores it back in the RAM. However, the Peters priority scheme cannot prioritize the order in which a plurality of counters stored in the RAM are to be updated when multiple simultaneous events occur, nor can it generate a priority signal to access the particular RAM memory location where the incremented count value is stored.
U.S. Pat. No. 4,341,950 titled, "Method and Circuitry for Synchronizing the Read and Update Functions of a Timer/Counter Circuit," and issued Jan. 24, 1980 to Ronald Kyles, discloses a synchronizing circuit which synchronizes the read and update functions of a counter circuit so that the read and update functions do not occur simultaneously. The Kyles circuit includes an N-bit counter and an N-bit storage register for storing the current count value of the counter. However, the system does not disclose means for incrementing a plurality of counters located in one storage device, for prioritizing the order in which the plurality of counters are to be incremented, or for addressing the memory location where a prioritized counter selected to incremented is located.
U.S Pat. No. 3,353,160 titled, "Tree Priority Circuit," and issued Nov. 14, 1967 to Arwin Linquist, teaches a tree priority circuit which receives several inputs in parallel and, through the use of logic gates, prioritizes the input signal. However, the Linquist patent does not disclose a system for incrementing a plurality of counters stored in one storage device or for generating an address signal to address the location where the prioritized counter is stored.
U.S. Pat. No. 3,597,641 titled, "Integrated Circuit Chips," and issued Aug. 3, 1971 to Neville Ayres, shows an integrated circuit chip having a separate storage element linked together by logic gates. Each of the separate storage elements is a counter. Similarly, U.S. Pat. No. 3,967,095 titled, "Multi-Counter Register," and issued June 29, 1976 to William Herring et al., discloses a register having a plurality of counters that count the electrical pulses that are generated from a plurality of sources wherein one counter is associated with each source. U.S. Pat. No. 4,206,346 titled, "System for Gathering Data Representing the Number of Event Occurrences," and issued June 3, 1980 to Toshio Hirosowa et al., reveals a system where a computer has a plurality of separate counters. The system counts the number of times that a plurality of events occur. However, the '641, '095 and '346 patents do not disclose a system wherein a single storage device is used to store the plurality of counters and which generates an access signal to access the location in the storage device where a particular counter is stored, where the access signal is based upon the priority in which the counters are to be accessed.
The memory based events counter of the present invention may be used in conjunction with a data transmission network, such as the Fiber Distributed Data Interface (FDDI), to monitor a plurality of systems events.
The Fiber Distributed Data Interface (FDDI) protocol is an American National Standard (ANS) for data transmission which applies to a 00 megabit/second token ring network that utilizes an optical fiber transmission medium The FDDI protocol is described in "FDDI-an Overview," Digests of Papers IEEE Computer Society Int'l Conf., Compcon '87, January, 1987, which is herein incorporated by reference.
The FDDI protocol is intended as a high performance interconnection among computers as well as among computers and their associated mass storage sub-systems and other peripheral equipment
Information is transmitted on an FDDI ring in "frames" that consist of a sequence of 5-bit data characters or "symbols " Information is typically transmitted in symbol pairs or "bytes." Tokens are used to signify the right to transmit data between stations.
A Physical function (PHY) provides the hardware connection to adjacent stations in an FDDI network; it provides the optical fiber hardware components that allow a link from one FDDI station to another. The Physical function simultaneously receives and transmits serial data. The Physical function's receiver receives the encoded serial data stream from a station or medium, establishes symbol boundaries based on the recognition of a start delimiter symbol pair, and transmits decoded symbols to its associated media access control function (MAC).